1. Field of the Invention
The invention relates to a semiconductor integrated circuit device such as a semiconductor memory.
2. Description of the Prior Art
Referring to FIG. 1, there is shown a typical layout of a semiconductor memory 11. The memory 11 is of a rectangle having a short side X and a long side Y, and a memory cell area 12 is provided inside. The memory area 12 occupies approximately 80 percent of the entire area. Reference designations 13A and 13B represent control areas where circuits for controlling the memory cell are provided. Input and output areas 14A and 14B are provided on the outside of the control areas 13A and 13B. In the input and output areas 14A and 14B, pads 15 and transistors P and N are provided along the short side X.
In the input and output areas 14A and 14B, an output circuit and an input circuit are provided. The output circuit includes, as shown in FIG. 6, a P-channel metal oxide semiconductor (MOS) transistor P and an N-channel MOS transistor N connected between a power supply line V.sub.DD and a reference potential point 8. The drains of the transistors P and N are connected to a pad PAD. In the input circuit, as shown in FIG. 7, the pad PAD is connected to the gates of the P-channel transistor P and the N-channel transistor N, and the drains are connected to a buffer 9 provided in the control areas 13A and 13B.
Referring to FIG. 2, there is shown the arrangement of the pads and MOS transistors in the input and output circuits of FIG. 1. For example, P2 and N2 on the left and right sides of a pad PAD2 respectively represent a P-channel MOS transistor and an N-channel MOS transistor of the circuit shown in FIG. 6 or 7. Thus, the pad PAD2 and the transistors P2 and N2 constitute a group of input or output circuits. Likewise, a pad PAD3 and transistors P3 and N3 constitute a group.
In this case, to avoid latch up (a phenomenon that two parasitic bipolar transistors of PNP and NPN types formed in an integrated circuit (IC) using complementary metal oxide semiconductor (CMOS) transistors are in thyrister operation state), the groups are arranged so that the P-channel MOS transistors and the N-channel MOS transistors are separately arranged from each other and that transistors of the same conductivity type (e.g. P1 and P2, N2 and N3, and P3 and P4) adjoin each other.
In the conventional memory layout, the integrated circuit density depends on a size L in the X direction of one output circuit (or input circuit) shown in FIG. 2, and the realization of a higher integrated circuit density is impossible. For this reason, although the size of the main part of the chip can be reduced like a small capacity memory using a fine process, the size (in particular, the size in the X direction) of the input and output circuit portion cannot be reduced. As a result, the size of the chip cannot be sufficiently reduced.
The same is true of a semiconductor integrated circuit device like a multi-output memory having a number of pads compared to the chip size. This problem also stems from the fact that although the technology to reduce the device sizes of transistors has advanced, the size of the pad cannot always be reduced because of the problem of the bonding of connecting wires. Incidentally, the size of the pad is 110 .mu.m.times.110 .mu.m.